`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 2023/12/28 17:45:15
// Design Name: 
// Module Name: cmp
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
`include "funct.vh"

module cmp(
    input wire [31:0] a,b,
    input wire [2:0] op,
	output wire y
    );
    wire eqs = (a == b);
    wire neqs = (a != b);
    wire gzs = (a[31] == 0 && a != {32{1'b0}}) ? 1 : 0 ;
    wire gezs = (a[31] == 0) ? 1 : 0;
    wire lzs = (a[31] == 1) ? 1 : 0;
    wire lezs = (a[31] == 1 || a == {32{1'b0}}) ? 1 : 0; 
    assign y = (op == `Sign_EQ) ? eqs :
                      (op == `Sign_NE) ? neqs :
                      (op == `Sign_GZ) ? gzs :
                      (op == `Sign_GEZ) ? gezs :
                      (op == `Sign_LZ) ? lzs : lezs;
endmodule
